1. Field of the Invention
The present invention is in the field of power converters. The present invention is further in the field of semiconductor switching power converters. The present invention further relates to the field of integrated synthetic ripple control methods for switching power converters and circuits. The present invention is further in the field of integrated switching power converters. The present invention is further in the field of minimum on- and off-time control types for switching power converters. The implementation is not limited to a specific technology, and applies to either the invention as an individual component or to inclusion of the present invention within larger systems which may be combined into larger integrated circuits.
2. Brief Description of Related Art
Modern electronic applications require power management devices that supply power to integrated circuits or more generally to complex loads. In general, power switching converters are becoming more and more important for their compact size, cost and efficiency. Switching power converters comprise isolated and non isolated topologies. The galvanic isolation is generally provided by the utilization of transformers. Although the subject invention is mainly focused on non isolated switching power converters, it refers both to isolated and non isolated power converters.
Modern switching power converters are in general divided in step down power converters, also commonly known as “buck converters”, and step up power converters commonly known as “boost converters”. This definition stems from the ability of the converter to generate regulated output voltages that are lower or higher than the input voltage regardless of the load applied.
One class of modern switching power converters implemented in integrated circuits is the one comprising hysteretic control or pseudo-hysteretic control where a synthetic ripple signal is generated and compared to a reference to determine the duty cycle of the switching period in order to regulate the output voltage at the desired level. These hysteretic power converters do not include an error amplifier, a specific compensation network or a periodic signal to determine the switching frequency.
In fact their switching frequency is determined by several factors like the input voltage, the output voltage, the toad, the output capacitor value, the inductor value, the hysteresis value, and the general propagation delays of the feedback network, of the comparator, of the driver, and of the output stage. Therefore, if left uncontrolled, the switching frequency of these power converters varies depending on the conditions of the converter.
However, typically, it is desirable to have constant switching frequency in continuous conduction mode for several reasons, but mainly to contain the harmonic content of the output stage switching and eventually to allow the filtering of electro-magnetic interference generated by the fast slew rate of the output nodes of the converter.
Although the imposition of a constant switching frequency somewhat alters the frequency response of the power converters and complicates the analysis and study of the stability of the regulator in presence of line and load transients, the switching frequency in hysteretic power converters is generally regulated and maintained constant by means of Phase Lock Loop (PLL), Frequency Lock Loop (FLL) or Delay Lock Loop (DLL) circuits. These circuits effectively modulate a loop parameter to regulate the switching frequency to be the same as the frequency of a provided clock signal.
FIG. 1 depicts a typical prior art block diagram of a hysteretic buck converter with switching frequency control. The oscillator 5 generates a clock signal operating at the desired frequency. The PLL block 4 compares the clock signal with the drive signal coming from the comparator and generates a voltage proportional to the error signal. The output of the PLL 4 is fed into a hysteresis control block 3 that modulates the hysteresis of the comparator 2 in order to regulate the switching frequency of the power converter to be the same as the one of the clock signal generated by the oscillator 5.
These frequency control circuits are clearly operating in closed loop and as such need to be frequency compensated to be locking as quickly as possible and be stable in all conditions. These requirements are often not trivial and the common outcome is that a PLL circuit typically requires several clock cycles to lock to a desired frequency. Furthermore these circuits are often affected by noise and present jitter or phase noise of the switching. A typical PLL requires a phase detector, a filter and a VCO (Voltage Controlled Oscillator).
In hysteretic power converters one of the most challenging transitions occurs when the load is abruptly switched on from a very light load to a heavy load condition. In this case the power converter should provide a relatively stable output voltage with minimum undershoot and a fast transition from DCM (Discontinuous Conduction Mode) to CCM (Continuous Conduction Mode) where the term Discontinuous or Continuous refers to the inductor current. When the load is very low the inductor current tends to reach the zero value within the switching period, while, when the load is high enough, the inductor current remains positive during the whole period.
In order to maintain high efficiency throughout all the load conditions, in DCM, the power converter needs to lower its switching frequency and to reduce, as much as possible, the current consumption of the integrated circuit. This reduction of power consumption is obtained by turning off various portions of the circuit and by slowing down (lowering the bias) the sections of the power converter that are required to continue functioning. The power converter does not need to regulate its switching frequency in DCM and it can operate in PFM (Pulse Frequency Modulation), therefore the frequency synchronization circuit is either turned off or significantly de-biased.
However when the transition to CCM is required, the frequency control circuit needs to turn on and possibly to lock to the desired switching frequency as quickly as possible in order to avoid uncontrolled switching and high magnitude EMI generation outside of the known controlled spectrum.
In the field of switching power converters, and in particular in the field of ripple regulators, it has been proposed the combined use of a minimum on-time approach with synthetic ripple signal generation. A prior art describing this approach is found in Wu et al. (US 2009/0174380) where the synthetic ripple signal, generated by a couple of transconductance amplifiers, is compared with the output of an error amplifier. This signal is then used to reset a Flip Flop (FF) and to generate the PWM signal to drive the power stage with the proper duty cycle. A clock signal is used to set the FF and to generate the minimum on-time. The power converter switches at the frequency of the clock signal.
However, the stability of this system is very difficult to study and, more importantly, to control. The gain of the system can at times be too high to guarantee a stable operation in all conditions. Another interesting prior art attempt to solve the problem is described in Lipcsei (U.S. Pat. No. 6,813,173). Lipcsei shows a hysteretic step down power converter controlled by a comparator whose inputs are the output of the power converter and a reference voltage composed of a DC part and of a ramp signal or periodic signal. The converter proposed by Lipcsei presents several drawbacks. Although the ramp signal may be at a constant frequency and although the power converter may switch at a constant frequency in Continuous Conduction Mode (CCM) in specific conditions, it does not maintain the desired switching frequency in all conditions.
Furthermore the output of the converter is subject to switching noise that could be even greater in amplitude than the superimposed voltage ripple and therefore the control of the converter may be very difficult to obtain even if the amplitude of the ramp in the reference voltage is large. Lastly the operation is not necessarily stable and, in fact Lipcsei introduces a not well defined stability circuit in the loop without teaching how that would function, but certainly the possibility for instability and sub-harmonics operation is quite high.
Another interesting prior art is described in Chen et al. (U.S. Pat. No. 7,202,642). Chen describes a hysteretic switching step down power converter where a synthetic ripple signal is summed to a reference voltage to be compared with the power converter output voltage. The ramp signal representative of the synthetic ripple signal is not a constant frequency ramp, therefore while this approach may be interesting because it may show a stable system with fast load transient response, it certainly does not teach how to obtain a high performing constant frequency switching power converter.
A further prior art is found in Stoichita (U.S. Pat. No. 7,482,793) where, a step down switching power converter with constant on-time and minimum off-time type of control is described. However, similarly to the case of Chen, this is not a constant frequency approach and in fact the major evidence of this is documented by the fact that no clock signal or oscillator is shown in the diagram or described in the specification of the patent. Although different, another example of similar prior art is found in Pullen et al. (U.S. Pat. No. 7,019,504). In this case two ramp signals are generated at both inputs of the comparator but since this is a constant on-time type of control, the switching frequency depends on the input voltage and other parameters, and it certainly does not represent a constant frequency power converter either.
Another interesting prior art is described in Groom et al. (U.S. Pat. No. 6,495,995) where a ripple multiphase step down power converter is depicted. In one of the drawings a virtual ripple signal is compared with a reference and the output of the comparator is processed by a not well defined switching control circuit. The switching frequency is not constant because a constant on-time type of approach is described. Furthermore no periodic clock signal or oscillator output is ever introduced nor described.
Finally the prior art Groom (U.S. Pat. No. 7,764,057) describes a hysteretic ramp added to the reference signal to be compared with the output voltage, but again this is not a constant frequency power converter demonstrated by the lack of clock signal or oscillator, and, in fact, the system described is a constant on-time buck converter.
All the cited prior art does not describe a constant frequency switching power converter with transient performance comparable to the one of the purely hysteretic approach and with method of controlling the system stability in all conditions. It is therefore a purpose of the present invention to describe a novel switching power converter that combines the characteristic of the hysteretic control with synthetic ripple generation but that operates at a desired constant frequency without the use of frequency control circuits, like a PLL, and with a simple and reliable means for controlling the stability of the system.
It is another purpose of the present invention to describe a power converter that can operate at constant and high switching frequency without the use of error amplifiers and compensation networks in the main loop. It is another purpose of the present invention to describe a constant frequency boost power converter that is stable and operating at high switching frequencies.